LogicEngine8 by joymonkey

This sketch is missing a short description
The is a WIP sketch for the RSeries Logic Engine. The current focus is to reduce the amount of SRAM usage during normal usage (the standard logic color patterns).

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<iframe style="height: 510px; width: 100%; margin: 10px 0 10px;" allowTransparency="true" src="https://codebender.cc/embed/sketch:53044" frameborder="0"></iframe>

Embed The Serial Monitor

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<iframe style="height: 510px; width: 100%; margin: 10px 0 10px;" allowTransparency="true" src="https://codebender.cc/embed/serialmonitor" frameborder="0"></iframe>